Ultrashallow junction formation and gate activation in deep-submicron CMOS

Download

PDF Restricted to Registered users only Download (190Kb)

Description/Abstract

This paper addresses the optimization of ion implantation and rapid thermal annealing for the
fabrication of shallow junctions and the activation of polycrystalline silicon gates in deepsubmicron
CMOS transistors. Achieving ultrashallow, low-resistance junctions was studied by
combining low-energy B and As implantation with spike annealing. In addition, experiments
using B doping marker superlattices were performed to identify the critical physical effects
underlying dopant activation and diffusion. The combination of high ramp rates (~100 oC/s) and
~1 s cycles at temperatures as high as 1100 °C can be used to improve dopant activation without
inducing significant thermal diffusion after TED has completed. MOS capacitors were used to
identify the implantation and annealing conditions needed for adequate activation of the gate
electrode. In comparison to the conventional recrystallized amorphous Si gates, it was found that
fine-grained poly-Si allows for the use of lower processing temperatures or shorter annealing
times while improving the gate activation level. The fine-grained crystal structure enhances the
de-activation of B dopants in PMOS gates during the thermal treatments following gate
activation. Yet, the resulting dopant loss stays within acceptable limits as verified by excellent
0.18 μm device performance. The feasibility of spike annealing and poly-Si gate materials for
100-nm technology was proven by full integration using gate lengths down to 80 n