Issues in the design of a logic simulator: element modelling for efficiency

Brown, A.D., Nichols, K.G. and Zwolinski, M. (1996) Issues in the design of a logic simulator: element modelling for efficiency. IEE proceedings on Circuits, Devices and Systems, IEE CD, (1), 21-27.


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The background for this paper is provided by a mixed signal circuit simulation package. Here, we discuss a number of issues that arose during the course of the logic model design and implementation. We describe a unique method of using inertial cancellation in the detection of set-up and hold time violations in flip-flops and other memory-like elements, and an effective technique of modelling sources so that each queues at most one event at any time. Results are presented showing a test circuit failing to operate correctly as a result of timing violations, correctly simulated by these modelling techniques.

Item Type: Other
ISSNs: 1350-2409
Divisions : Faculty of Physical Sciences and Engineering > Electronics and Computer Science > EEE
ePrint ID: 251280
Accepted Date and Publication Date:
February 1996Published
Date Deposited: 27 Oct 1999
Last Modified: 31 Mar 2016 13:51
Further Information:Google Scholar

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