Brown, A.D., Nichols, K.G. and Zwolinski, M.
Issues in the design of a logic simulator: element modelling for efficiency.
IEE proceedings on Circuits, Devices and Systems, IEE CD, (1), .
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The background for this paper is provided by a mixed signal circuit simulation package. Here, we discuss a number of issues that arose during the course of the logic model design and implementation. We describe a unique method of using inertial cancellation in the detection of set-up and hold time violations in flip-flops and other memory-like elements, and an effective technique of modelling sources so that each queues at most one event at any time. Results are presented showing a test circuit failing to operate correctly as a result of timing violations, correctly simulated by these modelling techniques.
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