HDL-specific source level behavioural optimisation
Nijhar, T.P.K. and Brown, A.D. (1997) HDL-specific source level behavioural optimisation. IEE Proceedings on Computers and Digital Techniques, IEE CD, (2), 138-144.
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Description/Abstract
Optimisation is a key facet of the behavioural synthesis problem. The process may be carried out at different levels in the processing, usually at the source© or datapath©level, or both. In a previous paper, we have reported a source level VHDL optimiser, which applies optimisation techniques derived from conventional sequential and parallel programming languages. This process produces structural descriptions that are up to 33% faster and 20% smaller than the corresponding 'brute force' mapping of behaviour to structure. In this paper, we describe a further set of optimisation transforms that may be applied at the source level to a VHDL behavioural description. These transforms have no conventional programming language counterpart, and are specific to hardware description languages. We have optimised a number of designs with respect to area and/or delay, with and without these transforms. The results show that with this extra class of transforms there is an improvement of around 44% in delay and 38% in area.
| Item Type: | Other |
|---|---|
| ISSNs: | 1350-2387 |
| Divisions: | Faculty of Physical and Applied Science > Electronics and Computer Science > EEE |
| Item ID: | 251282 |
| Date Deposited: | 27 Oct 1999 |
| Last Modified: | 02 Mar 2012 12:19 |
| Contributors: | Nijhar, T.P.K. (Author) Brown, A.D. (Author) |
| Date: | March 1997 |
| Status: | Published |
| Publisher: | IEE |
| Further Information: | Google Scholar |
| URI: | http://eprints.soton.ac.uk/id/eprint/251282 |
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