Reduction of latency and resource usage in bit-level pipelined data ptahs for FPGAs


Kollig, P. and Al-Hashimi, B.M. (1999) Reduction of latency and resource usage in bit-level pipelined data ptahs for FPGAs. 7th International Symposium on Field Programmable Gate Arrays, 1, (1), 227-34.

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Description/Abstract

Pipelining of data path structures increases the throughput rate at the expense of enlarged resource usage and latency unless architectures optimised towards specifice applications are used. This paper describes a novel methodology for the design of generic bit-level pipelined data paths that have the low resource usage and latency of specifically tailored architectures but still allow the fexiable trade-off between speed and resource requirements inherent in generic circuits. This is achieved through the elimination of all skew and alignment flip-flops from the data path whilst still maintaining the original pipelining scheme, hence allowing more compact structures with decreased circuit delays. The resulting low latency is beneficial in the realisation of all recursive signal processing applications and the reduced resource usage enables particularly the efficient FPGA realisation of high performance signal processing functions. The design process is illustrated through the high level-based FPGA realisation of a 9th-order wave digital filter, demonstrating that high performance and efficient resource usage are possible. For example, the implementation of a digital filter with 10-bit signal word length and 6-bit coefficients using a Xilinx XC4013XL-1 device supports sample rates of 2.5MHz

Item Type: Other
Additional Information: Organisation: ACM/SIGDA Address: USA
ISBNs: 1581130880
Divisions: Faculty of Physical Sciences and Engineering > Electronics and Computer Science > Electronic & Software Systems
ePrint ID: 251400
Date Deposited: 03 Apr 2000
Last Modified: 27 Mar 2014 19:52
Further Information:Google Scholar
URI: http://eprints.soton.ac.uk/id/eprint/251400

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