Mixed arithmetic architecture: a solution to the iteration bound for resources FPGA and CPLD recursive digital filters

Description/Abstract

This paper describes a bew approach for negating the iteration bound of recursive digital filters. The approach is based on first applying equivalence transforms to tyhe recursive section signal flow graph to determine the maximum allowable pipeline delay for each feedback loop and then selecting bit-parallel arithmetic where pipelined digit-serial computation does not meet these delay limits. Scattered look-ahead pipelining is considered in combination with the proposed method. The resultant structures remain predominantly digit-seral in operation, making the approach ideally suited to designs for programmable logic arrays since high resource efficiency is achieved. Using new digit-serial and bit-parallel multiplier offering reduced pipeline dealy, a 14-bit data path 11-bit coefficient biquad filter for the Xilinx CX4010 achieves 36Msample per sec processing rate, up to 5 times higher than previously reported results.