FPGA Implementation of high performance FIR Filters
Kollig, P. and Al-Hashimi, B.M. (1997) FPGA Implementation of high performance FIR Filters. UNSPECIFIED IEEE International Symposium on Circuits and Systems, 2240-43.
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Description/Abstract
This paper describes the design and implementation of high performance, high speed linear phase FIR filters using FPGA technology. To demonstrate the design process, the implementation of a 64 tap filter with 60dB attenuation at 0.28fs, 12dB attenuation at 0.25fs and a passband ripple of <0.02dB up to 0.22fs is included. The filter with 10bit signal and 8bit coefficients has been realised on a Xilinx XC4006E device and operates at a sampling frequency of 1.4MHz.
| Item Type: | Conference or Workshop Item (UNSPECIFIED) |
|---|---|
| Additional Information: | Address: IEEE |
| Divisions: | Faculty of Physical and Applied Science > Electronics and Computer Science > Electronic & Software Systems |
| ePrint ID: | 251503 |
| Deposited On: | 03 Nov 1999 |
| Last Modified: | 02 Mar 2012 12:18 |
| Further Information: | Google Scholar |
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