High performance distributed arithmetic FPGA decimators for video frequency applications

Description/Abstract

This paper describes a method for implementing high performance integer decimators for video-frequency applications using FPGAs. The decimators are derived from polyphase decomposition of an FIR filter prototype and implemented using a modified distributed arithemtic look-up table architecture previously only suitable for low-order specifications. A new pseudo floating point method of coefficient representation is described, allowing high-order filters to be achieved with the limited resources of FPGAs. Furthemore, a RAM based delay operator is used to provide an efficient decimator sample dealy section in place of the flip-flop realisation normally employed. To demonstrate the design methodology, the implementation of a 2:1 decimator for 27MHz oversampled video signals using a Xilinx XC4013E FPGA is included.