High performance distributed arithmetic FPGA decimators for video frequency applications
Living, J., AL-Hashimi, B.M. and Moniri, M. (1998) High performance distributed arithmetic FPGA decimators for video frequency applications. UNSPECIFIED IEEE International Conference on Circuits and Systems, 294-297.
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Description/Abstract
This paper describes a method for implementing high performance integer decimators for video-frequency applications using FPGAs. The decimators are derived from polyphase decomposition of an FIR filter prototype and implemented using a modified distributed arithemtic look-up table architecture previously only suitable for low-order specifications. A new pseudo floating point method of coefficient representation is described, allowing high-order filters to be achieved with the limited resources of FPGAs. Furthemore, a RAM based delay operator is used to provide an efficient decimator sample dealy section in place of the flip-flop realisation normally employed. To demonstrate the design methodology, the implementation of a 2:1 decimator for 27MHz oversampled video signals using a Xilinx XC4013E FPGA is included.
| Item Type: | Conference or Workshop Item (UNSPECIFIED) |
|---|---|
| Additional Information: | Address: USA |
| Divisions: | Faculty of Physical and Applied Science > Electronics and Computer Science > Electronic & Software Systems |
| Item ID: | 251545 |
| Date Deposited: | 03 Nov 1999 |
| Last Modified: | 02 Mar 2012 14:02 |
| Contributors: | Living, J. (Author) AL-Hashimi, B.M. (Author) Moniri, M. (Author) |
| Date: | September 1998 |
| Additional Information: | Address: USA |
| Status: | Published |
| Publisher: | IEEE International Conference on Circuits and Systems |
| Further Information: | Google Scholar |
| URI: | http://eprints.soton.ac.uk/id/eprint/251545 |
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