FPGA based video signal decimator for sample rate reduction from 28.64 to 14.32MHz
Living, J and Al-Hashimi, B.M. (1998) FPGA based video signal decimator for sample rate reduction from 28.64 to 14.32MHz. UNSPECIFIED IEE Colloquium on DSP: CAD, software and hardware.
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| Item Type: | Conference or Workshop Item (UNSPECIFIED) |
|---|---|
| Divisions: | Faculty of Physical and Applied Science > Electronics and Computer Science |
| Item ID: | 251546 |
| Date Deposited: | 03 Nov 1999 |
| Last Modified: | 01 Mar 2012 10:25 |
| Contributors: | Living, J (Author) Al-Hashimi, B.M. (Author) |
| Date: | October 1998 |
| Status: | Published |
| Publisher: | IEE Colloquium on DSP: CAD, software and hardware |
| Further Information: | Google Scholar |
| URI: | http://eprints.soton.ac.uk/id/eprint/251546 |
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