FPGA based video signal decimator for sample rate reduction from 28.64 to 14.32MHz

Living, J and Al-Hashimi, B.M. (1998) FPGA based video signal decimator for sample rate reduction from 28.64 to 14.32MHz.

Record type: Conference or Workshop Item (Other)

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More information

Published date: October 1998

Organisations: Electronics & Computer Science

Local EPrints ID: 251546

URI: http://eprints.soton.ac.uk/id/eprint/251546

PURE UUID: 14d42a4d-e385-4c18-965d-e840def5cd3b

Date deposited: 03 Nov 1999

Last modified: 10 Dec 2021 20:22

Author: J Living

Author: B.M. Al-Hashimi

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