CMOS Design of Group Delay Equaliser
Al-Hashimi, B.M., Dudek, F. and Sun, Y. (2000) CMOS Design of Group Delay Equaliser. UNSPECIFIED Kluwer Academic Publishers, Journal of Analog Integrated Circuits and Signal Processing, 163-169.
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Description/Abstract
Two new current-mode allpass sections based on dual-output OTAs and triple-output OTAs and grounded capacitors are described. Techniques to minimise the equaliser active device count and efficiently simulate grounded resistors are proposed. A 5th-order group delay equaliser based on the presented allpass sections is designed and simulated using multiple-output CMOS OTAs. Numercial optimisation is used to determine the equaliser order and parameters. SPICE simulation results are given demonstrating that the equaliser can effectively compensate the dealy characteristic of 4th-order 4MHz lowpass Chebyshev filter to <8ns ripple over 90% of the filter passband.
| Item Type: | Conference or Workshop Item (UNSPECIFIED) |
|---|---|
| Additional Information: | Address: USA |
| ISSNs: | 0925-1030 |
| Divisions: | Faculty of Physical and Applied Science > Electronics and Computer Science > Electronic & Software Systems |
| Item ID: | 251551 |
| Date Deposited: | 21 Jun 2000 |
| Last Modified: | 02 Mar 2012 13:17 |
| Contributors: | Al-Hashimi, B.M. (Author) Dudek, F. (Author) Sun, Y. (Author) |
| Date: | August 2000 |
| Additional Information: | Address: USA |
| Status: | Published |
| Publisher: | Kluwer Academic Publishers, Journal of Analog Integrated Circuits and Signal Processing |
| Further Information: | Google Scholar |
| URI: | http://eprints.soton.ac.uk/id/eprint/251551 |
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