Generation and Verification of Tests for Analogue Circuits Subject to Process Parameter Deviations
Spinks, S.J., Chalk, C.D., Zwolinski, M. and Bell, I.M. (1997) Generation and Verification of Tests for Analogue Circuits Subject to Process Parameter Deviations.
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| Item Type: | Other |
|---|---|
| Additional Information: | IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Organisation: IEEE |
| Divisions: | Faculty of Physical and Applied Science > Electronics and Computer Science > EEE |
| Item ID: | 251846 |
| Date Deposited: | 12 Nov 1999 |
| Last Modified: | 02 Mar 2012 11:57 |
| Contributors: | Spinks, S.J. (Author) Chalk, C.D. (Author) Zwolinski, M. (Author) Bell, I.M. (Author) |
| Date: | 1997 |
| Additional Information: | IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Organisation: IEEE |
| Status: | Published |
| Further Information: | Google Scholar |
| URI: | http://eprints.soton.ac.uk/id/eprint/251846 |
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