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Generation and Verification of Tests for Analogue Circuits Subject to Process Parameter Deviations

Generation and Verification of Tests for Analogue Circuits Subject to Process Parameter Deviations
Generation and Verification of Tests for Analogue Circuits Subject to Process Parameter Deviations
Spinks, S.J.
264634fb-7d9b-412c-83a1-5fdf5bd5fae0
Chalk, C.D.
896adf6a-641e-406d-9777-9a12ea51e4aa
Zwolinski, M.
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Bell, I.M.
ea8d42dd-d647-4e5a-a255-5e808300b7fa
Spinks, S.J.
264634fb-7d9b-412c-83a1-5fdf5bd5fae0
Chalk, C.D.
896adf6a-641e-406d-9777-9a12ea51e4aa
Zwolinski, M.
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Bell, I.M.
ea8d42dd-d647-4e5a-a255-5e808300b7fa

Spinks, S.J., Chalk, C.D., Zwolinski, M. and Bell, I.M. (1997) Generation and Verification of Tests for Analogue Circuits Subject to Process Parameter Deviations.

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More information

Published date: 1997
Additional Information: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Organisation: IEEE
Organisations: EEE

Identifiers

Local EPrints ID: 251846
URI: http://eprints.soton.ac.uk/id/eprint/251846
PURE UUID: c0d6e712-a1a9-4041-bb02-27ea3cbfc502
ORCID for M. Zwolinski: ORCID iD orcid.org/0000-0002-2230-625X

Catalogue record

Date deposited: 12 Nov 1999
Last modified: 09 Jan 2022 02:36

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Contributors

Author: S.J. Spinks
Author: C.D. Chalk
Author: M. Zwolinski ORCID iD
Author: I.M. Bell

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