A gate delay expression for the optimisation of ECL processes
Chor, E F, Brunnschweiler, A and Ashburn, P (1988) A gate delay expression for the optimisation of ECL processes. Journal of Solid State Circuits, SC-23, 251-259.
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| Item Type: | Other |
|---|---|
| Divisions: | Faculty of Physical and Applied Science > Electronics and Computer Science > NANO |
| Item ID: | 251863 |
| Date Deposited: | 15 Nov 1999 |
| Last Modified: | 02 Mar 2012 11:56 |
| Contributors: | Chor, E F (Author) Brunnschweiler, A (Author) Ashburn, P (Author) |
| Date: | 1988 |
| Status: | Published |
| Further Information: | Google Scholar |
| URI: | http://eprints.soton.ac.uk/id/eprint/251863 |
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