FPGA based video signal decimators for sample rate reduction from 27/28.64 MHz to 13.5/14.32 MHz
Living, J. and Al-Hashimi, B.M. (1999) FPGA based video signal decimators for sample rate reduction from 27/28.64 MHz to 13.5/14.32 MHz. UNSPECIFIED 8th International Symposium on Integrated Circuits, Devices and Systems (ISIC -99). Singapore, 38-42.
Download
Full text not available from this repository.
Description/Abstract
This paper describes the design and implementation of FPGA based decimator for 2:1 oversampled video signals. The maximum input data rate to be accommodated is 28.64Ms.s-1 for composite (YUV) signals while the most critical frequency response is defined by the CCIR 601 specification for luminance (Y) signals. An ossociated constant group delay characteristic is readilyb achieved by FIR filtering, leading to use of a polyphase network for decimation. The all-pass filters in the polyphase are realised using a distributed arithmetic architecture converted for digit-serial operation and a modular, resource efficent connection scheme for higher-order filters is considered. The decimators have been implemented using Xilinx XC4000E series FPGAs with -3 speed grade parts achieving sample processing rates of 30Ms.s[1, clearly meeting the required performance.
| Item Type: | Conference or Workshop Item (UNSPECIFIED) |
|---|---|
| Additional Information: | Organisation: IEEE, IEE |
| Divisions: | Faculty of Physical and Applied Science > Electronics and Computer Science > Electronic & Software Systems |
| Item ID: | 252023 |
| Date Deposited: | 03 Apr 2000 |
| Last Modified: | 02 Mar 2012 11:38 |
| Contributors: | Living, J. (Author) Al-Hashimi, B.M. (Author) |
| Date: | September 1999 |
| Additional Information: | Organisation: IEEE, IEE |
| Status: | Published |
| Publisher: | 8th International Symposium on Integrated Circuits, Devices and Systems (ISIC -99). Singapore |
| Further Information: | Google Scholar |
| URI: | http://eprints.soton.ac.uk/id/eprint/252023 |
Actions (login required)
 |
View Item |
