Architecture-mapped concurrent-transform programmable 2D FIR filters for serial image processing
Living, J and Al-Hashimi, B.M. (1999) Architecture-mapped concurrent-transform programmable 2D FIR filters for serial image processing. UNSPECIFIED 8th International Symposium on Integrated Circuits, Devices and Systems (ISIC-99), Singapore, 112-116.
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Description/Abstract
This paper presents a new approach to 2-D FIR filters using concurrent image transformation, negating pipeline delay penalties and reducing same-size convolution edge effects associated with sequential-transform filters realised in hardware while maintaining direct programmability. The new filters are suitable for FPGA and CPLD when a logic mapping technique is applied, which also maximises operational speed to provide video signal processing rates. An example 5-tap filter achieves 42 MHz clock frequency giving a 10.5 MHz pixel processing rate.
| Item Type: | Conference or Workshop Item (UNSPECIFIED) |
|---|---|
| Additional Information: | Organisation: IEEE, IEE |
| Divisions: | Faculty of Physical and Applied Science > Electronics and Computer Science > Electronic & Software Systems |
| ePrint ID: | 252217 |
| Deposited On: | 03 Apr 2000 |
| Last Modified: | 02 Mar 2012 12:38 |
| Further Information: | Google Scholar |
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