Characterisation of layout dependent thermal coupling in SOI CMOS current mirrors
Tenbroek, B. M., Redman-White, W., Lee, M. S. L., Bunyan, R. J. T., Uren, M. J. and Brunson, K. M. (1996) Characterisation of layout dependent thermal coupling in SOI CMOS current mirrors. IEEE Transactions on Electron Devices, 43, (12), 2227-2232.
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A current mirror is proposed as a suitable structure for the characterization of layout dependent thermal coupling between MOSFETs. Using current and voltage measurements, and compensating for series resistance effects, very small changes in local device temperature can be made visible. For the first time it is demonstrated that thermal coupling can be observed in a 2 um SOI CMOS technology, with devices separated by as much as 20 um. Measurements were verified by eletrothermal SPICE simulations, using a simple lumped model to express thermal coupling. The observations reinforce the need for accurate circuit level models, including self heating and thermal coupling effects, for analogue applications in VLSI SOI CMOS technologies.
|Divisions:||Faculty of Physical Sciences and Engineering > Electronics and Computer Science > NANO
|Date Deposited:||09 Sep 2004|
|Last Modified:||27 Mar 2014 19:55|
|Further Information:||Google Scholar|
|RDF:||RDF+N-Triples, RDF+N3, RDF+XML, Browse.|
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