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A silicon on sapphire MOSFET based on the calculation of surface potential

A silicon on sapphire MOSFET based on the calculation of surface potential
A silicon on sapphire MOSFET based on the calculation of surface potential
A circuit simulation model is presented suitable for the design of analogue and digital SOS MOSFET integrated circuits. Both the drift and diffusion components of channel current are modeled, which are computed from the surface potentials at the drain and source ends of the channel. The surface potential function varies continuously from subthreshold to strong inversion allowing a smooth transition of device conductances and capacitances at the threshold voltage. Charge is conserved in the model formulation yielding reliable simulation results in transient analysis. The model has been implemented in the SPICE program, together with important extrinsic elements such as impact ionization current, pn-junction current and capacitances, and substrate resistance. The pn-junction current expression includes a physical formulation for the drain leakage current. The influence of temperature on device characteristics is included, making the model valid from -55 to 125°C. Simulation results are compared with measured dc device characteristics showing considerable improvement over bulk MOS models in predicting the drain conductance. In subthreshold, the model predicts the observed increase in inverse subthreshold slope with drain bias for n-channel devices. Transient simulations show that capacitive coupling from drain, gate and source nodes can strongly influence the floating substrate potential. The model has been successfully applied to the design of analogue SOS circuits.
494 - 506
Howes, R.
24866d29-c7b9-4861-950b-a4a611fbba9b
Redman-White, W.
d5376167-c925-460f-8e9c-13bffda8e0bf
Nichols, K.G.
70f6440b-fc7c-4bbb-ac73-ef658fc947f3
Robinson, M.
967f55db-5b3c-46a3-8ea0-2e7c01de71f0
Bird, S.
7e1dd4cd-b781-4093-8bbb-a5ae9098e3b7
Mole, P.J.
83c15f2d-179e-47da-8455-c0cb67ab92c7
Howes, R.
24866d29-c7b9-4861-950b-a4a611fbba9b
Redman-White, W.
d5376167-c925-460f-8e9c-13bffda8e0bf
Nichols, K.G.
70f6440b-fc7c-4bbb-ac73-ef658fc947f3
Robinson, M.
967f55db-5b3c-46a3-8ea0-2e7c01de71f0
Bird, S.
7e1dd4cd-b781-4093-8bbb-a5ae9098e3b7
Mole, P.J.
83c15f2d-179e-47da-8455-c0cb67ab92c7

Howes, R., Redman-White, W., Nichols, K.G., Robinson, M., Bird, S. and Mole, P.J. (1994) A silicon on sapphire MOSFET based on the calculation of surface potential. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 13 (4), 494 - 506. (doi:10.1109/43.275359).

Record type: Article

Abstract

A circuit simulation model is presented suitable for the design of analogue and digital SOS MOSFET integrated circuits. Both the drift and diffusion components of channel current are modeled, which are computed from the surface potentials at the drain and source ends of the channel. The surface potential function varies continuously from subthreshold to strong inversion allowing a smooth transition of device conductances and capacitances at the threshold voltage. Charge is conserved in the model formulation yielding reliable simulation results in transient analysis. The model has been implemented in the SPICE program, together with important extrinsic elements such as impact ionization current, pn-junction current and capacitances, and substrate resistance. The pn-junction current expression includes a physical formulation for the drain leakage current. The influence of temperature on device characteristics is included, making the model valid from -55 to 125°C. Simulation results are compared with measured dc device characteristics showing considerable improvement over bulk MOS models in predicting the drain conductance. In subthreshold, the model predicts the observed increase in inverse subthreshold slope with drain bias for n-channel devices. Transient simulations show that capacitive coupling from drain, gate and source nodes can strongly influence the floating substrate potential. The model has been successfully applied to the design of analogue SOS circuits.

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More information

Published date: March 1994
Organisations: Nanoelectronics and Nanotechnology

Identifiers

Local EPrints ID: 253751
URI: http://eprints.soton.ac.uk/id/eprint/253751
PURE UUID: 65e00449-3dd4-48af-9a76-c928026c7454

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Date deposited: 07 Aug 2000
Last modified: 14 Mar 2024 05:28

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Contributors

Author: R. Howes
Author: W. Redman-White
Author: K.G. Nichols
Author: M. Robinson
Author: S. Bird
Author: P.J. Mole

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