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Simultaneous Optimisation of Dynamic Power, Area and Delay in Behavioural Synthesis

Simultaneous Optimisation of Dynamic Power, Area and Delay in Behavioural Synthesis
Simultaneous Optimisation of Dynamic Power, Area and Delay in Behavioural Synthesis
Concern over power dissipation coupled with the continuing rise in system size and complexity means that there is a growing need for high-level design tools capable of automatically optimising systems to take into account power dissipation, in addition to the more conventional metrics of area, delay and testability. Current methods for reducing power consumption tend to be ad-hoc: for example, slowing down, or turning off idle parts of the system, or a controlled reduction in power supply. The behavioural synthesis system described in this paper features an integrated incremental power estimation capability, which makes use of activity profiles, generated automatically through simulation of a design on any standard VHDL simulator; accurate circuit-level cell models (generated, again automatically, via Spice simulation); and a comprehensive system power model. This data, along with similar estimators for area and delay, guides the optimisation of a design towards independent, user-specified objectives for final area, delay, clock speed, and energy consumption. In addition, a range of power reducing features are included encompassing: supply voltage scaling, clock gating, input latching, input gating, low-power cells, and pipelined and multicycle units. These are automatically exploited during optimisation as part of the area/delay/power dissipation trade-off process. The resulting system is capable of reducing the estimated energy consumption of several benchmark designs by factors of between 3.5 and 7.0 times. Furthermore, the design exploration capability enables a range of alternative structural implementations to be generated from a single behavioural description, with differing area/delay/power trade-offs.
Williams, A.C.
4c566cf2-8942-410b-9741-eb4a90f7125f
Brown, A.D.
5c19e523-65ec-499b-9e7c-91522017d7e0
Zwolinski, M.
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Williams, A.C.
4c566cf2-8942-410b-9741-eb4a90f7125f
Brown, A.D.
5c19e523-65ec-499b-9e7c-91522017d7e0
Zwolinski, M.
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0

Williams, A.C., Brown, A.D. and Zwolinski, M. (2000) Simultaneous Optimisation of Dynamic Power, Area and Delay in Behavioural Synthesis.

Record type: Other

Abstract

Concern over power dissipation coupled with the continuing rise in system size and complexity means that there is a growing need for high-level design tools capable of automatically optimising systems to take into account power dissipation, in addition to the more conventional metrics of area, delay and testability. Current methods for reducing power consumption tend to be ad-hoc: for example, slowing down, or turning off idle parts of the system, or a controlled reduction in power supply. The behavioural synthesis system described in this paper features an integrated incremental power estimation capability, which makes use of activity profiles, generated automatically through simulation of a design on any standard VHDL simulator; accurate circuit-level cell models (generated, again automatically, via Spice simulation); and a comprehensive system power model. This data, along with similar estimators for area and delay, guides the optimisation of a design towards independent, user-specified objectives for final area, delay, clock speed, and energy consumption. In addition, a range of power reducing features are included encompassing: supply voltage scaling, clock gating, input latching, input gating, low-power cells, and pipelined and multicycle units. These are automatically exploited during optimisation as part of the area/delay/power dissipation trade-off process. The resulting system is capable of reducing the estimated energy consumption of several benchmark designs by factors of between 3.5 and 7.0 times. Furthermore, the design exploration capability enables a range of alternative structural implementations to be generated from a single behavioural description, with differing area/delay/power trade-offs.

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Published date: November 2000
Organisations: EEE

Identifiers

Local EPrints ID: 254052
URI: http://eprints.soton.ac.uk/id/eprint/254052
PURE UUID: c7b0206d-0721-4dba-8629-f1fa91aa7ef0
ORCID for M. Zwolinski: ORCID iD orcid.org/0000-0002-2230-625X

Catalogue record

Date deposited: 05 Jul 2001
Last modified: 15 Mar 2024 02:39

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Contributors

Author: A.C. Williams
Author: A.D. Brown
Author: M. Zwolinski ORCID iD

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