A VHDL Behavioural Synthesis System with Floating Point Support
Baidas, Z.A., Brown, A.D. and Williams, A.C. (2000) A VHDL Behavioural Synthesis System with Floating Point Support. UNSPECIFIED , 31-36.
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Description/Abstract
This paper describes an enhancement to the MOODS (Multiple Objective Optimisation in Data and control path Synthesis) behavioural VHDL synthesis system to support the processing of designs containing floating-point (and complex) arithmetic. In particular, the development of a floating-point module library and a floating-point optimiser capable of making strategic decisions about the high level binding of each floating-point operation in a way that meets the users pre-defined goal. The floating-point modules are based around either iterative generating techniques or lookup tables; either way, the scope of optimisation is considerable, especially when targeting limited architectures such as FPGAs.
| Item Type: | Conference or Workshop Item (UNSPECIFIED) |
|---|---|
| Additional Information: | Organisation: Forum on Design Languages 2000 (FDL 2000) |
| Divisions: | Faculty of Physical and Applied Science > Electronics and Computer Science > EEE |
| Item ID: | 254055 |
| Date Deposited: | 05 Jul 2001 |
| Last Modified: | 02 Mar 2012 11:57 |
| Contributors: | Baidas, Z.A. (Author) Brown, A.D. (Author) Williams, A.C. (Author) |
| Date: | September 2000 |
| Additional Information: | Organisation: Forum on Design Languages 2000 (FDL 2000) |
| Status: | Published |
| Further Information: | Google Scholar |
| URI: | http://eprints.soton.ac.uk/id/eprint/254055 |
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