Dynamic Memory Allocation in a VHDL Behavioural Synthesis System
Milton, D.J.D., Brown, A.D. and Williams, A.C. (2000) Dynamic Memory Allocation in a VHDL Behavioural Synthesis System. UNSPECIFIED , 45-52.
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VHDL is capable of describing the dynamic allocation of memory resources at �run-time�. This paper describes how this concept may be supported in a hardware synthesis environment. This requires a heap management system to be synthesised and implicitly accessed from within any user code, supporting the use of the VHDL access type. A method for controlling the storage of dynamic information (the heap manager) is reviewed. Issues such as timing and fragmentation are also discussed. An example of a design synthesised using the methods shown is reviewed last, which demonstrates the power of the technique.
|Item Type:||Conference or Workshop Item (UNSPECIFIED)|
|Additional Information:||Organisation: Forum on Design Languages 2000 (FDL 2000)|
|Divisions:||Faculty of Physical Sciences and Engineering > Electronics and Computer Science > EEE
|Date Deposited:||05 Jul 2001|
|Last Modified:||27 Mar 2014 19:56|
|Further Information:||Google Scholar|
|RDF:||RDF+N-Triples, RDF+N3, RDF+XML, Browse.|
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