SiGe device architectures synthesised by local area Ge implantation; structural and electrical characterisation


Graoui, H., Nejim, A., Hemment, P.L.F., Riley, L., Mitchell, M. and Ashburn, P. (2000) SiGe device architectures synthesised by local area Ge implantation; structural and electrical characterisation. Proceedings of Ion Implantation Technology Conference

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Description/Abstract

SiGe device islands have been synthesised by Ge+ ion implantation of doses of 0.45 x 1016Ge+/cm2 to 4.05 x1016Ge+/cm2 at 100keV or 200keV into patterned (100) bulk silicon wafers. The control of 'mask edge defects' and 'end of range' defects has been achieved by applying Si+ post-amorphisation, where the ions are implanted into a wider window, and by using solid phase epitaxial regrowth. Defect free SiGe alloy islands with a peak Ge concentration of ~6at% and minority carrier generation lifetimes comparible to bulk silicon (~ms) have been successfully produced. The integration of this synthesis process into CMOS and bipolar technologies is discussed. Realization of shallower islands, with dimensions more consistent with future generations of advanced devices and with higher Ge contents, is in hand.

Item Type: Conference or Workshop Item (UNSPECIFIED)
Divisions: Faculty of Physical Sciences and Engineering > Electronics and Computer Science > NANO
ePrint ID: 255699
Date Deposited: 02 Apr 2001
Last Modified: 27 Mar 2014 19:57
Further Information:Google Scholar
ISI Citation Count:0
URI: http://eprints.soton.ac.uk/id/eprint/255699

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