Architctural synthesis of high-level analogue VHDL-AMS descriptions using netlist extraction from parse trees
Asensi, G.D., Kazmierski, T.J. and Merino, R.R. (2000) Architctural synthesis of high-level analogue VHDL-AMS descriptions using netlist extraction from parse trees. Electronics Letters, v 36, , (20), 1680-1682.
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| Item Type: | Article |
|---|---|
| ISSNs: | 0013-5194 |
| Divisions: | Faculty of Physical and Applied Science > Electronics and Computer Science > EEE |
| Item ID: | 255719 |
| Date Deposited: | 11 Apr 2001 |
| Last Modified: | 02 Mar 2012 12:20 |
| Contributors: | Asensi, G.D. (Author) Kazmierski, T.J. (Author) Merino, R.R. (Author) |
| Date: | September 2000 |
| Status: | Published |
| Publisher: | IEE |
| Further Information: | Google Scholar |
| URI: | http://eprints.soton.ac.uk/id/eprint/255719 |
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