A Technique for Transparent Fault Injection and Simulation in VHDL
Zwolinski, M. (2000) A Technique for Transparent Fault Injection and Simulation in VHDL. Small System Simulation Symposium (SSSS)
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A technique is described for the automatic insertion of fault models into VHDL gate models, using shared variables and linked lists. This procedure does not require any modification to the structural description of a circuit using these models. A method for automatic sequential fault simulation is further demonstrated.
|Item Type:||Conference or Workshop Item (UNSPECIFIED)|
|Divisions:||Faculty of Physical Sciences and Engineering > Electronics and Computer Science > EEE
|Date Deposited:||17 Apr 2001|
|Last Modified:||27 Mar 2014 19:57|
|Further Information:||Google Scholar|
|RDF:||RDF+N-Triples, RDF+N3, RDF+XML, Browse.|
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