SiGe CMOS Fabrication using SiGe MBE and Anodic/LTO Gate Oxide
Sidek, R M, Straube, U N, Waite, A M, Evans, A G R, Parry, C, Phillips, P, Whall, T E and Parker, E H C (2001) SiGe CMOS Fabrication using SiGe MBE and Anodic/LTO Gate Oxide. Semiconductor Science and Technology
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Description/Abstract
An investigation of a SiGe CMOS process fulfilling low thermal budget requirements was carried out. Three different updoped layers were grown successively by MBE: 1 20 nm buffer layer, a 15 nm SiGe layer and a 15 nm cap layer. The Ge concentration of the SiGe layer was either uniform 20% or linearly graded 0 - 40% from the substrate to the surface. A 50 nm thick undoped Si layer was grown for the reference devices. Anodic oxide and LTO were used ase gate dielectrics. The annealing was performed at relatively modest temperatures. The SiGe p-MOSFETs were compared to the Si reference devices. We report an enhancement of the hole mobility up to 70% for the SiGe p-MOSFETs.
| Item Type: | Article |
|---|---|
| Divisions: | Faculty of Physical and Applied Science > Electronics and Computer Science > NANO |
| Item ID: | 255763 |
| Date Deposited: | 01 May 2001 |
| Last Modified: | 02 Mar 2012 13:18 |
| Contributors: | Sidek, R M (Author) Straube, U N (Author) Waite, A M (Author) Evans, A G R (Author) Parry, C (Author) Phillips, P (Author) Whall, T E (Author) Parker, E H C (Author) |
| Date: | 1 May 2001 |
| Status: | Unpublished |
| Further Information: | Google Scholar |
| URI: | http://eprints.soton.ac.uk/id/eprint/255763 |
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