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SiGe CMOS Fabrication using SiGe MBE and Anodic/LTO Gate Oxide

SiGe CMOS Fabrication using SiGe MBE and Anodic/LTO Gate Oxide
SiGe CMOS Fabrication using SiGe MBE and Anodic/LTO Gate Oxide
An investigation of an SiGe CMOS process fulfilling low-thermal-budget requirements was carried out. Three different undoped layers were grown successively by MBE: a 20 nm buffer layer, a 15 nm SiGe layer and a 15 nm cap layer, The Ge concentration of the SiGe layer was either uniform 20% or linearly graded 0-40% from the substrate to the surface. A 50 nm thick undoped Si layer was grown for the reference devices. Anodic oxide and LTO were used as gate dielectrics. The annealing was performed at relatively modest temperatures. The SiGe p-MOSFETs were compared to the Si reference devices. We report an enhancement of the hole mobility up to 70% for the SiGe p-MOSFETs.
0268-1242
135-138
Sidek, R M
aa58196f-9739-4999-bc2e-e99dd4a63903
Straube, U N
f83df843-cd85-4d4e-8ddd-73d77b9c9215
Waite, A M
d021f13b-f8dd-4398-89d1-bb9cf308072c
Evans, A G R
c4a3f208-8fd9-491d-870f-ce7eef943311
Parry, C
4997087f-4955-4069-b88a-abcdcc14be67
Phillips, P
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Whall, T E
875dbadb-3f0d-4706-8496-19c5ab15e162
Parker, E H C
e64c94b4-1029-4f6d-9ff2-6d305907f79c
Sidek, R M
aa58196f-9739-4999-bc2e-e99dd4a63903
Straube, U N
f83df843-cd85-4d4e-8ddd-73d77b9c9215
Waite, A M
d021f13b-f8dd-4398-89d1-bb9cf308072c
Evans, A G R
c4a3f208-8fd9-491d-870f-ce7eef943311
Parry, C
4997087f-4955-4069-b88a-abcdcc14be67
Phillips, P
e069de2a-3e86-44e6-b2d3-8084c6b312e2
Whall, T E
875dbadb-3f0d-4706-8496-19c5ab15e162
Parker, E H C
e64c94b4-1029-4f6d-9ff2-6d305907f79c

Sidek, R M, Straube, U N, Waite, A M, Evans, A G R, Parry, C, Phillips, P, Whall, T E and Parker, E H C (2000) SiGe CMOS Fabrication using SiGe MBE and Anodic/LTO Gate Oxide. Semiconductor Science and Technology, 15 (2), 135-138. (doi:10.1088/0268-1242/15/2/310).

Record type: Article

Abstract

An investigation of an SiGe CMOS process fulfilling low-thermal-budget requirements was carried out. Three different undoped layers were grown successively by MBE: a 20 nm buffer layer, a 15 nm SiGe layer and a 15 nm cap layer, The Ge concentration of the SiGe layer was either uniform 20% or linearly graded 0-40% from the substrate to the surface. A 50 nm thick undoped Si layer was grown for the reference devices. Anodic oxide and LTO were used as gate dielectrics. The annealing was performed at relatively modest temperatures. The SiGe p-MOSFETs were compared to the Si reference devices. We report an enhancement of the hole mobility up to 70% for the SiGe p-MOSFETs.

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More information

Published date: 2000
Organisations: Nanoelectronics and Nanotechnology

Identifiers

Local EPrints ID: 255771
URI: http://eprints.soton.ac.uk/id/eprint/255771
ISSN: 0268-1242
PURE UUID: 57920542-2e61-493e-8c3c-6969a5e04dd1

Catalogue record

Date deposited: 01 May 2001
Last modified: 14 Mar 2024 05:34

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Contributors

Author: R M Sidek
Author: U N Straube
Author: A M Waite
Author: A G R Evans
Author: C Parry
Author: P Phillips
Author: T E Whall
Author: E H C Parker

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