Temporal Logic Model Checking of CSP: Tools and Techniques
Leuschel, Michael, Wolton, Ivan, Massart, Thierry and Adhianto, Laksono (2001) Temporal Logic Model Checking of CSP: Tools and Techniques. Proceedings of the Workshop on Automated Verification of Critical Systems (AVOCS'01) Oxford University Computing Laboratory.
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Description/Abstract
We study the possibility of doing LTL model checking on CSP specifications in the context of refinement. We present a technique to perform LTL model checking of CSP processes using refinement checking in general and the FDR tool in particular. We present a tool which automates the translation process from LTL model checking to CSP refinement. Also, if time permits, we will present another tool which uses latest generation Prolog technology to symbolically animate, compile, and model check CSP specifications.
| Item Type: | Conference or Workshop Item (UNSPECIFIED) |
|---|---|
| Additional Information: | Technical Report. |
| Divisions: | Faculty of Physical and Applied Science > Electronics and Computer Science |
| Item ID: | 255930 |
| Date Deposited: | 15 Jun 2001 |
| Last Modified: | 02 Mar 2012 13:18 |
| Contributors: | Leuschel, Michael (Author) Wolton, Ivan (Author) Massart, Thierry (Author) Adhianto, Laksono (Author) Nowak, David (Editor) |
| Date: | April 2001 |
| Additional Information: | Technical Report. |
| Status: | Published |
| Publisher: | Oxford University Computing Laboratory |
| Further Information: | Google Scholar |
| URI: | http://eprints.soton.ac.uk/id/eprint/255930 |
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