A New BIST Methodology for Fully-Balanced OTA-C Filters
A New BIST Methodology for Fully-Balanced OTA-C Filters
Abstract - This paper proposes a new BIST structural testing methodology for fully-balanced OTA-C filters. The methodology is based on using a simple group-delay equaliser to emulate the function of the filter under test; any discrepancies resulting from comparing the filter and equaliser outputs indicates a faulty circuit. The test circuitry is designed using detailed analysis of the possible faults and their effects on the filter output, ensuring high fault coverage and minimisation of test accuracy dependence on manufacturing process variations. Furthermore, most of the test circuitry is digital, the analogue part requires only a single low-precision capacitor, and the frequency of the test stimulus does not need to be exact. Using simulation it has shown been that up to 98.6% fault coverage is possible when the proposed methodology is applied to a 4.5MHz Chebyshev low pass filter used as a test vehicle. The complete CMOS design of the self-testable filter is included. From actual layout, the estimated test circuitry area overhead is 20% which compares well with recently reported results.
Wilcock, R.
039894e9-f32d-49e0-9ebd-fb13bc489feb
Al-Hashimi, B. M.
0b29c671-a6d2-459c-af68-c4614dce3b5d
July 2002
Wilcock, R.
039894e9-f32d-49e0-9ebd-fb13bc489feb
Al-Hashimi, B. M.
0b29c671-a6d2-459c-af68-c4614dce3b5d
Wilcock, R. and Al-Hashimi, B. M.
(2002)
A New BIST Methodology for Fully-Balanced OTA-C Filters.
IEEE International Symposium on Circuits and Systems, Phoenix, Arizona.
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Abstract
Abstract - This paper proposes a new BIST structural testing methodology for fully-balanced OTA-C filters. The methodology is based on using a simple group-delay equaliser to emulate the function of the filter under test; any discrepancies resulting from comparing the filter and equaliser outputs indicates a faulty circuit. The test circuitry is designed using detailed analysis of the possible faults and their effects on the filter output, ensuring high fault coverage and minimisation of test accuracy dependence on manufacturing process variations. Furthermore, most of the test circuitry is digital, the analogue part requires only a single low-precision capacitor, and the frequency of the test stimulus does not need to be exact. Using simulation it has shown been that up to 98.6% fault coverage is possible when the proposed methodology is applied to a 4.5MHz Chebyshev low pass filter used as a test vehicle. The complete CMOS design of the self-testable filter is included. From actual layout, the estimated test circuitry area overhead is 20% which compares well with recently reported results.
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Published date: July 2002
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IEEE International Symposium on Circuits and Systems, Phoenix, Arizona, 2002-07-01
Organisations:
Electronic & Software Systems, EEE
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Local EPrints ID: 255961
URI: http://eprints.soton.ac.uk/id/eprint/255961
PURE UUID: b3afec63-3660-4013-8605-28b375bf75a2
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Date deposited: 26 Jan 2004
Last modified: 14 Mar 2024 05:36
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Author:
R. Wilcock
Author:
B. M. Al-Hashimi
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