Si/Si0.64Ge0.36/Si pMOSFETs with Enhanced Voltage Gain and Low 1/f Noise
Prest, M. J., Palmer, M. J., Braithwaite, G., Grasby, T. J., Phillips, P. J., Mironov, O. A., Parker, E. H. C., Whall, T. E., Waite, A. M. and Evans, A. G. R. (2001) Si/Si0.64Ge0.36/Si pMOSFETs with Enhanced Voltage Gain and Low 1/f Noise.
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Description/Abstract
Si/Si0.64Fe0.36/Si p MOSFETs with written gate lengths in the range 0.5mu micron to 10mu micron have been fabricated in a reduced thermal budget variant of a standard CMOS process. The devices exhibit enhanced maximum voltage-gains and reduced 1/f noise as compared to silicon controls.
| Item Type: | Other |
|---|---|
| Additional Information: | Organisation: ESSDERC 2001 |
| Divisions: | Faculty of Physical and Applied Science > Electronics and Computer Science > NANO |
| Item ID: | 256168 |
| Date Deposited: | 10 Dec 2001 |
| Last Modified: | 02 Mar 2012 14:02 |
| Contributors: | Prest, M. J. (Author) Palmer, M. J. (Author) Braithwaite, G. (Author) Grasby, T. J. (Author) Phillips, P. J. (Author) Mironov, O. A. (Author) Parker, E. H. C. (Author) Whall, T. E. (Author) Waite, A. M. (Author) Evans, A. G. R. (Author) |
| Date: | 2001 |
| Additional Information: | Organisation: ESSDERC 2001 |
| Status: | Published |
| Further Information: | Google Scholar |
| URI: | http://eprints.soton.ac.uk/id/eprint/256168 |
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