Analysing trade-offs in scan power and test data compression for Systems-on-a-chip
Rosinger, P, Gonciari, P, Al-Hashimi, B.M and Nicolici, Nicola (2002) Analysing trade-offs in scan power and test data compression for Systems-on-a-chip. UNSPECIFIED IEE Proceedings: Computers and Digital Techniques.
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Description/Abstract
This paper investigates the relationship between test data compression and power dissipation during scan testing. Trade-off analysis using ISCAS89 benchmark circuits show that by employing the recently proposed symmetric coding scheme and varying a weighting parameter in the W-SLR algorithm, the embedded core designer can explicitly control the scan power and volume of test data.
| Item Type: | Conference or Workshop Item (UNSPECIFIED) |
|---|---|
| Divisions: | Faculty of Physical and Applied Science > Electronics and Computer Science > Electronic & Software Systems |
| Item ID: | 256510 |
| Date Deposited: | 10 Jun 2002 |
| Last Modified: | 02 Mar 2012 11:57 |
| Contributors: | Rosinger, P (Author) Gonciari, P (Author) Al-Hashimi, B.M (Author) Nicolici, Nicola (Author) |
| Date: | August 2002 |
| Status: | Published |
| Publisher: | IEE Proceedings: Computers and Digital Techniques |
| Further Information: | Google Scholar |
| ISI Citation Count: | 12 |
| URI: | http://eprints.soton.ac.uk/id/eprint/256510 |
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