Automated high level synthesis of hardware building blocks present in ART--based neural networks, from VHDL--AMS descriptions
Lopez, J. A., Asensi, G. D., Ruiz, R. and Kazmierski, T.J. (2002) Automated high level synthesis of hardware building blocks present in ART--based neural networks, from VHDL--AMS descriptions. Proc. ISCAS'2002
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Description/Abstract
This contribution presents a VHDL--AMS model from a building block present in multichannel neural network based on the adaptive resonnance theory, and its automated synthesis using VHDL--AMS to hspice netlist translator. This building block shows continous dynamic behaviour, and it is complex enough to check the functionality of our translator. Both simulations, behavioural high level based on the VHDL--AMS model and structural based on SPICE automatically synthesized description, have been done in order to check the matching between the SPICE netlist synthesized againts its VHDL--AMS model.
| Item Type: | Conference or Workshop Item (UNSPECIFIED) |
|---|---|
| Divisions: | Faculty of Physical Sciences and Engineering > Electronics and Computer Science > EEE |
| Item ID: | 256523 |
| Date Deposited: | 25 Apr 2002 |
| Last Modified: | 02 Mar 2012 13:18 |
| Contributors: | Lopez, J. A. (Author) Asensi, G. D. (Author) Ruiz, R. (Author) Kazmierski, T.J. (Author) |
| Date: | May 2002 |
| Status: | Published |
| Further Information: | Google Scholar |
| ISI Citation Count: | 0 |
| URI: | http://eprints.soton.ac.uk/id/eprint/256523 |
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