Behavioural Fault Modelling using VHDL-AMS and Slow Transient Analysis with hAMSter Simulator to Speed-up Analogue Fault Simulation
Kilic, Yavuz and Zwolinski, Mark (2002) Behavioural Fault Modelling using VHDL-AMS and Slow Transient Analysis with hAMSter Simulator to Speed-up Analogue Fault Simulation. European Test Workshop
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Description/Abstract
Two of techniques to speed-up analogue fault simulation are: fault dropping/collapsing, in which faults that have similar circuit responses compared with the fault-free circuit response and/or with another faulty circuit response are considered equivalent; and behavioural/macro modelling, whereby parts of the circuit are modelled at a more abstract level, therefore reducing the complexity and the simulation time. This paper discusses behavioural modelling as a way to speed-up fault simulation for analogue circuits. In this paper, a new behavioural fault model is developed in VHDL-AMS for a CMOS operational amplifier circuit using slow transient analysis. Simulation results confirm up to 373 times speed-up in terms of CPU time.
| Item Type: | Conference or Workshop Item (UNSPECIFIED) |
|---|---|
| Additional Information: | Organisation: IEEE |
| Divisions: | Faculty of Physical and Applied Science > Electronics and Computer Science > EEE |
| Item ID: | 256640 |
| Date Deposited: | 28 Jun 2002 |
| Last Modified: | 02 Mar 2012 13:18 |
| Contributors: | Kilic, Yavuz (Author) Zwolinski, Mark (Author) |
| Date: | May 2002 |
| Additional Information: | Organisation: IEEE |
| Status: | Published |
| Further Information: | Google Scholar |
| URI: | http://eprints.soton.ac.uk/id/eprint/256640 |
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