Integrated Test Data Decompression and Core Wrapper Design for Low-Cost System-on-a-Chip Testing

Gonciari, Paul Theo, Al-Hashimi, Bashir and Nicolici, Nicola Nicolici (2002) Integrated Test Data Decompression and Core Wrapper Design for Low-Cost System-on-a-Chip Testing. Proceedings IEEE International Test Conference (ITC)

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This paper discusses an integrated solution for reducing the volume of test data for deterministic system-on-a-chip testing. The proposed solution is based on a new test data decompression architecture which exploits the features of a core wrapper design algorithm targeting the elimination of useless test data. The compressed test data can be transferred from the automatic test equipment to the on-chip decompression architecture using only one test pin, thus providing an efficient reduced pin count test methodology for multiple scan chains-based embedded cores. In addition to reducing the volume of test data, the proposed solution decreases the control overhead, test application time and power dissipation during scan. Further, it also requires lower on-chip area when compared to the testing scenarios which employ decompression architectures for every scan chain and it eliminates the synchronization overhead between the automatic test equipment and the system-on-a-chip. Moreover, the proposed solution is scalable and programmable and, since it can be considered as an add-on to a test access mechanism of a given width, it provides seamless integration with any design flow. Thus, the proposed integrated solution is an efficient low-cost test methodology for systems-on-a-chip.

Item Type: Conference or Workshop Item (UNSPECIFIED)
Additional Information: To appear Address: Baltimore, MD
Divisions : Faculty of Physical Sciences and Engineering > Electronics and Computer Science > Electronic & Software Systems
ePrint ID: 256729
Accepted Date and Publication Date:
October 2002Published
Date Deposited: 17 Sep 2002
Last Modified: 31 Mar 2016 13:57
Further Information:Google Scholar

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