Scheduling and Mapping of Conditional Task Graphs for the Synthesis of Low Power Embedded Systems


Wu, D., Al-Hashimi, B. M. and Eles, P. (2003) Scheduling and Mapping of Conditional Task Graphs for the Synthesis of Low Power Embedded Systems. Design, Automation and Test in Europe, Munich, Germany, 03 - 07 Mar 2003. , 90-95.

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Description/Abstract

This paper describes a new Dynamic Voltage Scaling (DVS) technique for embedded systems expressed as Conditional Task Graphs (CTGs). The idea is to identify and exploit the available worst case slack time, taking into account the conditional behaviour of CTGs. Also we examine the effect of combining a genetic algorithm based mapping with the DVS technique for CTGs and show that further energy reduction can be obtained. The techniques have been tested on a number of CTGs including a real-life example. The results show that the DVS technique can be applied to CTGs with energy saving up to 24%. Furthermore it is shown that savings of up to 51% are achieved by considering DVS during the mapping.

Item Type: Conference or Workshop Item (UNSPECIFIED)
Additional Information: Event Dates: 3-7 March 2003
Divisions: Faculty of Physical Sciences and Engineering > Electronics and Computer Science > Electronic & Software Systems
ePrint ID: 257386
Date Deposited: 06 May 2003
Last Modified: 27 Mar 2014 19:59
Further Information:Google Scholar
ISI Citation Count:2
URI: http://eprints.soton.ac.uk/id/eprint/257386

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