Power-conscious test synthesis and scheduling
Nicolici, Nicola and Al-Hashimi, Bashir M (2002) Power-conscious test synthesis and scheduling. IEEE Proceedings of Design and Test of Computers, 20, (4), 48-55.
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Description/Abstract
BIST increases circuit activity and hence power in data path circuits. The voltage drop that occurs during testing causes some good circuits to fail the testing process, leading to unnecessary manufacturing yield loss. Addressing this problem, the authors show how test synthesis and scheduling affect power dissipation and present new power-conscious algorithms.
| Item Type: | Article |
|---|---|
| Additional Information: | A preliminary version of this paper has won "Besaung Best Paper Award", IEEE International Test Conference 2000 |
| ISSNs: | 0740-7475 |
| Keywords: | Low power VLSI test |
| Divisions: | Faculty of Physical and Applied Science > Electronics and Computer Science > Electronic & Software Systems |
| Item ID: | 258330 |
| Date Deposited: | 10 Oct 2003 |
| Last Modified: | 02 Mar 2012 11:38 |
| Contributors: | Nicolici, Nicola (Author) Al-Hashimi, Bashir M (Author) |
| Date: | July 2002 |
| Additional Information: | A preliminary version of this paper has won "Besaung Best Paper Award", IEEE International Test Conference 2000 |
| Status: | Published |
| Publisher: | IEEE Computer Society |
| Further Information: | Google Scholar |
| URI: | http://eprints.soton.ac.uk/id/eprint/258330 |
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