A high speed dual modulus divider in SOI CMOS with stacked current steering phase selection architecture
Mistry, K., Redman-White, W., Benson, J. and D'Halleweyn, N.V. (2003) A high speed dual modulus divider in SOI CMOS with stacked current steering phase selection architecture. In, Proceedings of RF Integrated Circuit Symposium, Philadelphia, USA, , 471-474.
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Description/Abstract
This work describes a high frequency dual modulus divider designed and fabricated in a 0.35/spl mu/m PDSOI process, employing a stacked topology phase switching scheme. SOI CMOS technology is exploited to allow current re-use in a higher supply voltage than dictated by single device breakdown. Measurements show the circuit operating at 3GHz (Vdd = 6.8V).
| Item Type: | Conference or Workshop Item (Paper) |
|---|---|
| Additional Information: | Event Dates: 2003 |
| Divisions: | Faculty of Physical and Applied Science > Electronics and Computer Science > NANO |
| Item ID: | 259844 |
| Date Deposited: | 06 Sep 2004 |
| Last Modified: | 02 Mar 2012 13:20 |
| Contributors: | Mistry, K. (Author) Redman-White, W. (Author) Benson, J. (Author) D'Halleweyn, N.V. (Author) |
| Date: | 2003 |
| Additional Information: | Event Dates: 2003 |
| Status: | Published |
| Further Information: | Google Scholar |
| URI: | http://eprints.soton.ac.uk/id/eprint/259844 |
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