A Novel Switch-Current Phase Locked Loop


Wilcock, Reuben, Wilson, Peter R. and Al-Hashimi, Bashir (2005) A Novel Switch-Current Phase Locked Loop. At ISCAS 2005, Kobe, Japan,

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Description/Abstract

This paper investigates the design of phase locked loops (PLLs) using the switched current (SI) technique and proposes a novel 2nd order PLL architecture that does not require an explicit phase detector, unlike conventional PLL circuits. Simulated results based on 0.35m BSim3v3 CMOS models of two PLL designs (10MHz FSK demodulator, 500MHz frequency synthesizer) are included.

Item Type: Conference or Workshop Item (Poster)
Additional Information: Event Dates: May 2005
Divisions: Faculty of Physical Sciences and Engineering > Electronics and Computer Science > Electronic & Software Systems
Faculty of Physical Sciences and Engineering > Electronics and Computer Science > EEE
ePrint ID: 260404
Date Deposited: 28 Jan 2005
Last Modified: 27 Mar 2014 20:03
Further Information:Google Scholar
URI: http://eprints.soton.ac.uk/id/eprint/260404

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