Issues in the design of a logic simulator: an improved caching technique for event-queue management
Brown, AD, Nichols, KG and Zwolinski, M (1995) Issues in the design of a logic simulator: an improved caching technique for event-queue management. IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS, 142, (5), 293-298.
Full text not available from this repository.
The paper describes certain issues relevant to the development of a logic simulation engine, designed to be incorporated into a mixed-signal simulator. Usually, the rate-limiting process in any mixed-signal simulation is the analogue processing but, for systems with a significant asymmetry between logic and analogue components, the efficiency of the logic engine can obviously become important. A technique is reported for improving both the space and time complexity of the logic engine: a method of event-queue searching using multiple cache pointers. Experimental results show that about five cache pointers provide the optimum efficiency gain from this technique. Finally, problems of event-queue management are reviewed, with particular reference to the situation where simulation time is represented by a real number, as it must be in a mixed-signal environment.
|Keywords:||LOGIC SIMULATORS, EVENT QUEUE MANAGEMENT|
|Divisions:||Faculty of Physical and Applied Science > Electronics and Computer Science > EEE
|Date Deposited:||03 Feb 2005|
|Last Modified:||08 Aug 2012 23:45|
|Contributors:||Brown, AD (Author)
Nichols, KG (Author)
Zwolinski, M (Author)
|Further Information:||Google Scholar|
|ISI Citation Count:||1|
|RDF:||RDF+N-Triples, RDF+N3, RDF+XML, Browse.|
Actions (login required)