A Programmable Time Measurement Architecture for Embedded Memory Characterization

Collins, Matthew, Al-Hashimi, Bashir and Ross, Neil (2005) A Programmable Time Measurement Architecture for Embedded Memory Characterization. In, 10th IEEE European Test Symposium (ETS'05), Tallinn, Estonia, 22 - 25 May 2005. , 128-133.


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This paper describes a programmable time measurement architecture that facilitates memory characterization. We have created a novel standalone time measurement architecture that can measure rise time, fall time, pulse width and propagation delay time measurements without the need of additional circuitry [1] or circuit duplication [2]. This is achieved by the use of Time-to-Digital Conversion (TDC) based on the dual-slope principle. The key feature of the proposed architecture is programmability through the use of a novel programmable input stage. Furthermore, a current steering Time-to-Voltage Converter (TVC) is used in order to improve the linearity and dynamic range as compared to recent designs. The proposed architecture has been designed using 0.18m CMOS process and results from simulations using foundry models suggest it is possible to achieve a timing resolution of 103ps. The measurement core size is 110m x 75m.

Item Type: Conference or Workshop Item (Paper)
Additional Information: Event Dates: 22-25 May
Divisions: Faculty of Physical Sciences and Engineering > Electronics and Computer Science > Electronic & Software Systems
ePrint ID: 260640
Date Deposited: 01 Jun 2005
Last Modified: 27 Mar 2014 20:03
Further Information:Google Scholar
ISI Citation Count:0
URI: http://eprints.soton.ac.uk/id/eprint/260640

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