CMOS-compatible vertical MOSFETs and logic gates with reduced parasitic capacitance.
Kunz, V D, de Groot, C H, Gili, E, Uchino, T, Hall, S and Ashburn, P (2004) CMOS-compatible vertical MOSFETs and logic gates with reduced parasitic capacitance. At 34th European Solid State Device Research Conference (ESSDERC), Leuven, Belgium, 21 - 23 Sep 2004. , 221-224.
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| Item Type: | Conference or Workshop Item (Speech) |
|---|---|
| Additional Information: | Event Dates: 21-23 September |
| Divisions: | Faculty of Physical and Applied Science > Electronics and Computer Science > NANO |
| Item ID: | 260762 |
| Date Deposited: | 14 Apr 2005 |
| Last Modified: | 18 Aug 2012 03:58 |
| Contributors: | Kunz, V D (Author) de Groot, C H (Author) Gili, E (Author) Uchino, T (Author) Hall, S (Author) Ashburn, P (Author) |
| Date: | September 2004 |
| Additional Information: | Event Dates: 21-23 September |
| Status: | Published |
| Further Information: | Google Scholar |
| ISI Citation Count: | 2 |
| URI: | http://eprints.soton.ac.uk/id/eprint/260762 |
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