Strained-Si n-MOS surface-channel and buried Si0.7Ge0.3 compressively-strained p-MOS fabricated in a 0.25 mum heterostructure CMOS process
Paul, D.J., Temple, M., Olsen, S.H., ONeill, A.G., Tang, Y.T., Waite, A.M., Cerrina, C., Evans, A.G.R., Li, X., Zhang, J., Norris, D.J. and Cullis, A.G. (2005) Strained-Si n-MOS surface-channel and buried Si0.7Ge0.3 compressively-strained p-MOS fabricated in a 0.25 mum heterostructure CMOS process. Materials Science in Semiconductor Processing, 8, (1-3), 343-346.
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A 0.25 mum complimentary metal oxide semiconductor (CMOS) process has been used to fabricate surface channel strained-Si n-MOS devices and buried, compressively-strained-Si0.7Ge0.3 channel p-MOS. Enhancements in performance of on-current, transconductance and mobility over bulk, relaxed Si CMOS devices are demonstrated for both n- and p-MOS devices for all gate lengths fabricated from 0.1 up to 10 mum. The performance is compared to surface channel strained-Si CMOS which is superior to the buried channel results. Possible reasons are discussed. (C) 2004 Elsevier Ltd. All rights reserved.
|Keywords:||CMOS, strained-Si, SiGe|
|Divisions:||Faculty of Physical and Applied Science > Electronics and Computer Science > NANO
|Date Deposited:||17 May 2005|
|Last Modified:||02 Mar 2012 13:20|
|Contributors:||Paul, D.J. (Author)
Temple, M. (Author)
Olsen, S.H. (Author)
ONeill, A.G. (Author)
Tang, Y.T. (Author)
Waite, A.M. (Author)
Cerrina, C. (Author)
Evans, A.G.R. (Author)
Li, X. (Author)
Zhang, J. (Author)
Norris, D.J. (Author)
Cullis, A.G. (Author)
|Publisher:||Elsevier Sci Ltd, Oxford|
|Further Information:||Google Scholar|
|RDF:||RDF+N-Triples, RDF+N3, RDF+XML, Browse.|
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