Strained-Si n-MOS surface-channel and buried Si_0.7Ge_0.3 compressively-strained p-MOS fabricated in a 0.25 µm heterostructure CMOS process

Paul, D.J., Temple, M., Olsen, S.H., ONeill, A.G., Tang, Y.T., Waite, A.M., Cerrina, C., Evans, A.G.R., Li, X., Zhang, J., Norris, D.J. and Cullis, A.G. (2005) Strained-Si n-MOS surface-channel and buried Si_0.7Ge_0.3 compressively-strained p-MOS fabricated in a 0.25 µm heterostructure CMOS process. Materials Science in Semiconductor Processing, 8 (1-3), 343-346.

Abstract

A 0.25 µm complimentary metal oxide semiconductor (CMOS) process has been used to fabricate surface channel strained-Si n-MOS devices and buried, compressively-strained-Si_0.7Ge_0.3 channel p-MOS. Enhancements in performance of on-current, transconductance and mobility over bulk, relaxed Si CMOS devices are demonstrated for both n- and p-MOS devices for all gate lengths fabricated from 0.1 up to 10 µm. The performance is compared to surface channel strained-Si CMOS which is superior to the buried channel results. Possible reasons are discussed.

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