Minimizing Test Power in SRAM through Reduction of Pre-charge Activity
DILILLO, L., ROSINGER, P., AL-HASHIMI, B. M. and GIRARD, P. (2006) Minimizing Test Power in SRAM through Reduction of Pre-charge Activity. In, DATE - Design Automation and Test in Europe, Munich, Germany, 06 - 10 Mar 2006.
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Description/Abstract
In this paper we analyze the test power of SRAM memories and demonstrate that the full functional pre-charge activity is not necessary during test mode because of the predictable addressing sequence. We exploit this observation in order to minimize power dissipation during test by eliminating the unnecessary power consumption associated with the pre-charge activity. This is achieved through a modified pre-charge control circuitry, exploiting the first degree of freedom of March tests, which allows choosing a specific addressing sequence. The efficiency of the proposed solution is validated through extensive Spice simulations.
| Item Type: | Conference or Workshop Item (Paper) |
|---|---|
| Additional Information: | Event Dates: 6-10 March 2006 |
| Keywords: | Test, SRAM, low power, DfT, March Test, Pre-charge |
| Divisions: | Faculty of Physical and Applied Science > Electronics and Computer Science > Electronic & Software Systems |
| Item ID: | 261644 |
| Date Deposited: | 13 Dec 2005 |
| Last Modified: | 20 Aug 2012 03:46 |
| Contributors: | DILILLO, L. (Author) ROSINGER, P. (Author) AL-HASHIMI, B. M. (Author) GIRARD, P. (Author) |
| Date: | 2006 |
| Additional Information: | Event Dates: 6-10 March 2006 |
| Status: | Published |
| Further Information: | Google Scholar |
| ISI Citation Count: | 0 |
| URI: | http://eprints.soton.ac.uk/id/eprint/261644 |
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- Minimizing Test Power in SRAM through Reduction of Pre-charge Activity. (deposited 13 Dec 2005) [Currently Displayed]
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