On-chip time measurement architecture with femtosecond timing resolution

Collins, Matthew and Al-Hashimi, Bashir M. (2006) On-chip time measurement architecture with femtosecond timing resolution. 11th IEEE European Test Symposium (ETS'06), , Southampton, United Kingdom. 21 - 25 May 2006. 6 pp . (doi:10.1109/ETS.2006.36).

Record type: Conference or Workshop Item (Paper)

Abstract

This paper presents a new on-chip time measurement architecture which is based on the time-to-digital conversion (TDC) method that is capable of achieving a timing resolution of tens of femtoseconds without the use of external automatic test equipment (ATE). This is the highest temporal resolution that has been reported to-date and is achieved by the use of the homodyne technique. The proposed architecture has been designed using a 0.12mum CMOS process and simulation results based on foundry transistor models indicates that it is possible to achieve a timing resolution of 40 fs. The time measurement architecture is standalone and occupies a small silicon area, 150mum by 180mum, making it attractive for high resolution on-chip time measurement.

Text

collinsm_timemeasurement_ets06 - Accepted Manuscript

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