Ravel-XL: a hardware accelerator for assigned-delay compiled-code logic gate simulation


Riepe, M. A., Marques-Silva, J. P., Sakallah, K. A. and Brown, R. B. (1996) Ravel-XL: a hardware accelerator for assigned-delay compiled-code logic gate simulation. IEEE Transactions on VLSI Systems, 4, (1), 113-129.

Item Type: Article
Divisions: Faculty of Physical Sciences and Engineering > Electronics and Computer Science
ePrint ID: 262044
Date :
Date Event
March 1996Published
Date Deposited: 02 Mar 2006
Last Modified: 31 Mar 2016 14:04
Further Information:Google Scholar
URI: http://eprints.soton.ac.uk/id/eprint/262044

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