Ravel-XL: a hardware accelerator for assigned-delay compiled-code logic gate simulation


Riepe, M. A., Marques-Silva, J. P., Sakallah, K. A. and Brown, R. B. (1996) Ravel-XL: a hardware accelerator for assigned-delay compiled-code logic gate simulation. IEEE Transactions on VLSI Systems, 4, (1), 113-129.

Item Type: Article
Divisions: Faculty of Physical Sciences and Engineering > Electronics and Computer Science
ePrint ID: 262044
Date Deposited: 02 Mar 2006
Last Modified: 27 Mar 2014 20:05
Further Information:Google Scholar
ISI Citation Count:0
URI: http://eprints.soton.ac.uk/id/eprint/262044

Actions (login required)

View Item View Item

Downloads from ePrints over the past year. Other digital versions may also be available to download e.g. from the publisher's website.

View more statistics