Ravel-XL: a hardware accelerator for assigned-delay compiled-code logic gate simulation
Riepe, M. A., Marques-Silva, J. P., Sakallah, K. A. and Brown, R. B. (1996) Ravel-XL: a hardware accelerator for assigned-delay compiled-code logic gate simulation. IEEE Transactions on VLSI Systems, 4, (1), 113-129.
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| Item Type: | Article |
|---|---|
| Divisions: | Faculty of Physical and Applied Science > Electronics and Computer Science |
| Item ID: | 262044 |
| Date Deposited: | 02 Mar 2006 |
| Last Modified: | 02 Mar 2012 11:39 |
| Contributors: | Riepe, M. A. (Author) Marques-Silva, J. P. (Author) Sakallah, K. A. (Author) Brown, R. B. (Author) |
| Date: | March 1996 |
| Status: | Published |
| Publisher: | IEEE Press |
| Further Information: | Google Scholar |
| ISI Citation Count: | 0 |
| URI: | http://eprints.soton.ac.uk/id/eprint/262044 |
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