Enhancing Delay Fault Coverage through Low Power Segmented Scan

Zhang, Zhuo, M. Reddy, Sudhakar, Pomeranz, Irith, Rajski, Janusz and M. Al-Hashimi, Bashir (2006) Enhancing Delay Fault Coverage through Low Power Segmented Scan. 11th IEEE European Test Symposium, Southampton, UK, 21-24 May 2006

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Reducing power dissipation during test has been an active area of academic and industrial research for the last few years and numerous low power DFT techniques and test generation procedures have been proposed. Segmented scan [17-20] has been shown to be an effective technique in addressing test power issues in industrial designs [18]. To achieve higher shipped product quality, tests for delay faults are becoming essential components of manufacturing test. This paper demonstrates, for the first time, that segmented scan facilitates increased delay fault coverage without degrading the reduction of the switching activity obtained by segmented scan. The increased transition delay fault coverage is achieved through careful selection of the capture cycle application. Experimental results on larger ISCAS-89 benchmarks show that using three segments, on average, fault coverage using launch off capture can be increased by about 5.4% while simultaneously reducing the peak switching activity caused by capture cycles by over 30%.

Item Type: Article
Keywords: Low power test, DFT, delay test
Divisions : Faculty of Physical Sciences and Engineering > Electronics and Computer Science > Electronic & Software Systems
ePrint ID: 262097
Accepted Date and Publication Date:
May 2006Published
Date Deposited: 21 Mar 2006
Last Modified: 31 Mar 2016 14:04
Low-Power Built-in-Self-Test (LOBIST)
Funded by: EPSRC (GR/S05557/01)
1 April 2003 to 30 September 2006
Further Information:Google Scholar
URI: http://eprints.soton.ac.uk/id/eprint/262097

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