Effects of neglecting carrier tunneling on electrostatic potential in calculating direct tunneling gate current in deep submicron MOSFETs


Hakim, MMA and Haque, A (2002) Effects of neglecting carrier tunneling on electrostatic potential in calculating direct tunneling gate current in deep submicron MOSFETs. IEEE Transaction on Electron Devices, 49, (9), 1669-1671.

Download

[img] PDF
Download (230Kb)

Description/Abstract

We investigate the validity of the assumption of neglecting carrier tunneling effects on self-consistent electrostatic potential in calculating direct tunneling gate current in deep submicron MOSFETs. Comparison between simulated and experimental results shows that for accurate modeling of direct tunneling current, tunneling effects on potential profile need to be considered. The relative error in gate current due to neglecting carrier tunneling is higher at higher gate voltages and increases with decreasing oxide thickness. We also study the direct tunneling gate current in MOSFETs with high- gate dielectrics.

Item Type: Article
ISSNs: 1011092002802650
Divisions: Faculty of Physical Sciences and Engineering > Electronics and Computer Science > NANO
ePrint ID: 262447
Date Deposited: 02 May 2006
Last Modified: 27 Mar 2014 20:05
Further Information:Google Scholar
ISI Citation Count:6
URI: http://eprints.soton.ac.uk/id/eprint/262447

Actions (login required)

View Item View Item

Downloads from ePrints over the past year. Other digital versions may also be available to download e.g. from the publisher's website.

View more statistics