On-chip timing measurement architecture with femtosecond resolution
Collins, Matthew, Al-Hashimi, Bashir and Wilson, Peter (2006) On-chip timing measurement architecture with femtosecond resolution. Electronics Letters, 42, (9), 528-530.
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Description/Abstract
A new timing measurement architecture based on the time-to-digital conversion technique is presented. The architecture occupies a small silicon area (200x185um) in a 0.12um CMOS Process and can achieve tens of femtoseconds timing resolution, which is the highest reported to date.
| Item Type: | Article |
|---|---|
| Divisions: | Faculty of Physical and Applied Science > Electronics and Computer Science > Electronic & Software Systems Faculty of Physical and Applied Science > Electronics and Computer Science > EEE |
| ePrint ID: | 262543 |
| Deposited On: | 11 May 2006 |
| Last Modified: | 01 Mar 2012 22:57 |
| Further Information: | Google Scholar |
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