On-chip timing measurement architecture with femtosecond resolution


Collins, Matthew, Al-Hashimi, Bashir and Wilson, Peter (2006) On-chip timing measurement architecture with femtosecond resolution. Electronics Letters, 42, (9), 528-530.

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Description/Abstract

A new timing measurement architecture based on the time-to-digital conversion technique is presented. The architecture occupies a small silicon area (200x185um) in a 0.12um CMOS Process and can achieve tens of femtoseconds timing resolution, which is the highest reported to date.

Item Type: Article
Divisions: Faculty of Physical Sciences and Engineering > Electronics and Computer Science > Electronic & Software Systems
Faculty of Physical Sciences and Engineering > Electronics and Computer Science > EEE
Item ID: 262543
Date Deposited: 11 May 2006
Last Modified: 26 Apr 2013 03:41
Contributors: Collins, Matthew (Author)
Al-Hashimi, Bashir (Author)
Wilson, Peter (Author)
Date: April 2006
Status: Published
Further Information:Google Scholar
ISI Citation Count:1
URI: http://eprints.soton.ac.uk/id/eprint/262543

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