Exploiting Power-Area Tradeoffs in Behavioural Synthesis through clock and operations throughput selection
Ochoa-Montiel, M A, Al-Hashimi, B M and Kollig, P (2007) Exploiting Power-Area Tradeoffs in Behavioural Synthesis through clock and operations throughput selection. At ASPDAC, 23 - 27 Jan 2007.
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Description/Abstract
This paper describes a new dynamic-power aware High Level Synthesis (HLS) data path approach that considers the close interrelation between clock choice and operations throughput selection whilst attempting to minimize area, power, or a combination thereof. It is shown that the proposed approach with its compound cost function and its novel clock and operations throughput selection algorithm, obtains solutions with lower power and area than using previous relevant work [11]. Moreover, different power-area tradeoffs can be explored due to the appropriate choice of clock period and operations throughput using our novel approach.
| Item Type: | Conference or Workshop Item (Speech) |
|---|---|
| Additional Information: | Event Dates: 23 -27 January |
| Divisions: | Faculty of Physical and Applied Science > Electronics and Computer Science > Electronic & Software Systems |
| Item ID: | 263209 |
| Date Deposited: | 24 Nov 2006 |
| Last Modified: | 21 Aug 2012 03:41 |
| Contributors: | Ochoa-Montiel, M A (Author) Al-Hashimi, B M (Author) Kollig, P (Author) |
| Date: | 2007 |
| Additional Information: | Event Dates: 23 -27 January |
| Status: | Published |
| Further Information: | Google Scholar |
| ISI Citation Count: | 4 |
| URI: | http://eprints.soton.ac.uk/id/eprint/263209 |
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- Exploiting Power-Area Tradeoffs in Behavioural Synthesis through clock and operations throughput selection. (deposited 24 Nov 2006) [Currently Displayed]
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