A Technology for Building Shallow Junction MOSFETs on Vertical Pillar Walls
Tan, L., Buiu, O., Hall, S., Gili, E. and Ashburn, P. (2006) A Technology for Building Shallow Junction MOSFETs on Vertical Pillar Walls. At 8th International Conference on Solid-State and Integrated-Circuit Technology, Shanghai, China,
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| Item Type: | Conference or Workshop Item (Poster) |
|---|---|
| Additional Information: | Event Dates: October |
| Divisions: | Faculty of Physical and Applied Science > Electronics and Computer Science > NANO |
| Item ID: | 263253 |
| Date Deposited: | 18 Dec 2006 |
| Last Modified: | 02 Mar 2012 12:59 |
| Contributors: | Tan, L. (Author) Buiu, O. (Author) Hall, S. (Author) Gili, E. (Author) Ashburn, P. (Author) |
| Date: | 2006 |
| Additional Information: | Event Dates: October |
| Status: | Published |
| Further Information: | Google Scholar |
| URI: | http://eprints.soton.ac.uk/id/eprint/263253 |
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