On-Chip Time Measurement Architecture with Femtosecond Timing Resolution

Description/Abstract

This paper presents a new on-chip time measurement architecture which is based on the Time-to-Digital Conversion (TDC) method that is capable of achieving a timing resolution of tens of femtoseconds without the use of external automatic test equipment (ATE). This is the highest temporal resolution that has been reported to-date and is achieved by the use of the homodyne technique. The proposed architecture has been designed using a 0.12um CMOS process and simulation results based on foundry transistor models indicates that it is possible to achieve a timing resolution of 40 fs. The time measurement architecture is standalone and occupies a small silicon area, 150um by 180um, making it attractive for high resolution on-chip time measurement.