Shallow junctions on pillar sidewalls for sub-100nm vertical MOSFETs
Gili, E., Uchino, T., Hakim, M.M.A., Hall, S. and Ashburn, P. (2006) Shallow junctions on pillar sidewalls for sub-100nm vertical MOSFETs. IEEE Electron Device Letters, 27, (8), 692-695.
A simple process is described for the fabrication of a shallow drain junction on a pillar sidewall in sub-100nm vertical MOSFETs. The key feature of this process is the creation of a polysilicon spacer around the perimeter of the pillar to connect the channel to a polysilicon drain contact. The depth of the junction on the pillar sidewall is primarily determined by the thickness of the polysilicon spacer. This process is CMOS compatible, and hence facilitates the integration of a sub-100nm vertical MOSFET in a planar CMOS technology using mature lithography. The fabricated transistors have a sub-threshold slope of 95mV/dec (at VDS =1V) and a DIBL of 0.12V.
|Divisions:||Faculty of Physical and Applied Science > Electronics and Computer Science > NANO
|Date Deposited:||03 Jan 2007|
|Last Modified:||02 Mar 2012 11:39|
|Contributors:||Gili, E. (Author)
Uchino, T. (Author)
Hakim, M.M.A. (Author)
Hall, S. (Author)
Ashburn, P. (Author)
|Further Information:||Google Scholar|
|RDF:||RDF+N-Triples, RDF+N3, RDF+XML, Browse.|
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