A technology for building shallow junction MOSFETs on vertical pillar walls
Tan, L., Buiu, O., Hall, S., Gili, E. and Ashburn, P. (2006) A technology for building shallow junction MOSFETs on vertical pillar walls. At 8th International Conference on Solid State Electronics & Integrated Technology, Shanghai, China, 23 - 26 Oct 2006.
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Description/Abstract
This work addresses a fundamental problem of vertical MOSFETS, that is, inherently deep junctions that exacerbate short channel effects (SCE). A self-aligned oxide region, or junction stop (JS) is formed at the top of the pillar and the shallow drain junction is then formed by out-diffusion from an overlying poly-crystalline drain contact region. The efficacy of the approach is demonstrated by simulation and the influence of the JS on SCE clearly shown. The process has been used to produce experimental devices that are characterized and discussed in the context of the modeling.
| Item Type: | Conference or Workshop Item (Speech) |
|---|---|
| Additional Information: | Event Dates: October 23rd - 26th |
| Divisions: | Faculty of Physical and Applied Science > Electronics and Computer Science > NANO |
| Item ID: | 263286 |
| Date Deposited: | 03 Jan 2007 |
| Last Modified: | 02 Mar 2012 13:20 |
| Contributors: | Tan, L. (Author) Buiu, O. (Author) Hall, S. (Author) Gili, E. (Author) Ashburn, P. (Author) |
| Date: | 2006 |
| Additional Information: | Event Dates: October 23rd - 26th |
| Status: | Published |
| Further Information: | Google Scholar |
| URI: | http://eprints.soton.ac.uk/id/eprint/263286 |
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