Zwolinski, M and Reeve, JS
Behavioural synthesis of an adaptive Viterbi decoder.
In, DSPenabledRadio, 2005. The 2nd IEE/EURASIP Conference on, Southampton, UK,
19 - 20 Sep 2004.
The synthesis of a hardware implementation of a Viterbi decoder from a behavioural specification is discussed. This is applied to a parallelized version of a BCH decoder. A parameterizable high-level VHDL model of the parallel decoder has been developed. Scalability of the parallel decoder in hardware is demonstrated. An extension of this technique to an adaptive decoder is discussed.
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