Behavioural synthesis of an adaptive Viterbi decoder

Zwolinski, M and Reeve, JS (2005) Behavioural synthesis of an adaptive Viterbi decoder. In, DSPenabledRadio, 2005. The 2nd IEE/EURASIP Conference on, Southampton, UK, 19 - 20 Sep 2004. IEE.


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The synthesis of a hardware implementation of a Viterbi decoder from a behavioural specification is discussed. This is applied to a parallelized version of a BCH decoder. A parameterizable high-level VHDL model of the parallel decoder has been developed. Scalability of the parallel decoder in hardware is demonstrated. An extension of this technique to an adaptive decoder is discussed.

Item Type: Conference or Workshop Item (Paper)
Additional Information: Event Dates: SEP 19-20, 2004
ISSNs: 0537-9989
Divisions : Faculty of Physical Sciences and Engineering > Electronics and Computer Science > EEE
ePrint ID: 263415
Accepted Date and Publication Date:
Date Deposited: 12 Feb 2007
Last Modified: 31 Mar 2016 14:07
Further Information:Google Scholar

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